Flip flop setup, hold & metastability explorer tool

A educational / research implementation of the Avalanche consensus algorithm written in Rust

GEM-Standalone (GEMS3K) Solver of Chemical Equilibria for Coupled Simulation Codes

GEM-Selektor graphical user interface (GEMSGUI)

Library for the analysis of time-evolving graphs

EDA tool for characterizing the metastability resolution time constant (Tau) of bistable circuits

This repository contains the code and data to reproduce the results and figures from the study: Daniel Koch, Ulrike Feudel, Aneta Koseska (2025). Criticality governs response dynamics and entrainment of periodically forced ghost cycles. Physical Review E, XX: XXXX–XXXX.

Code from the study "Ghost channels and ghost cycles guiding long transients in dynamical systems"

A mathematical framework for measuring the dynamics of consciousness. The framework uses a composite index of scale-free temporal organisation, cross-frequency organisation, and metastability.

UVM-based SystemVerilog testbench for CDC & Async FIFO: SVA assertions, functional coverage, agents/sequences/scoreboard, and VCS/Questa run scripts.

This is a vhdl implementation of a toggle-level handshake for clock crossing domains.

Simulation scripts used in the study "Separation of sticker-spacer energetics governs the coalescence of metastable biomolecular condensates"

Hardware button debouncer with metastability protection - VHDL synchronizer chains and CDC fundamentals for reliable input handling

SRFM Quantum Phase13: Adaptive Transport Phase Memory and Persistent Topology-Only Structural Memory

Adaptive basin geometry, metastable topology-memory basins, and perturbation-driven structural memory dynamics in SRFM Quantum systems.

SRFM Quantum Phase15: Adaptive Structural Survival Metrics and Metastable Basin Dynamics

Asynchronous FIFO with CDC Reliability Analyzer built from scratch in Verilog. Gray-code pointers, 2-FF synchronizers, randomized stress testbench, timing closure on Artix-7 (WNS = +6.31 ns). No IP cores used.

Production-ready asynchronous FIFO buffer with independent read/write clock domains for safe CDC operations. Features Gray code pointers, dual flip-flop synchronizers, metastability prevention, and parameterized design. Essential for SoC inter-module communication and multi-clock systems.

Asynchronous FIFO design and verification in SystemVerilog based on Clifford Cummings’ “Simulation and Synthesis Techniques for Asynchronous FIFO Design,” using Gray code pointers that are synchronized into a different clock domain before testing for FIFO full or FIFO empty conditions.

Hardware-constrained validation of SRFM metastable structural diagnostics on IBM Quantum systems.